Presentation
Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes
DescriptionIn VLSI design, accurate pre-routing timing prediction is paramount. Traditional machine learning-based methods require extensive data, posing challenges for advanced technology nodes due to the time-consuming data preparation. To mitigate this issue, we propose a novel transfer learning framework that uses data from previous nodes for learning on the target node. Our method initially disentangles and aligns timing path features across different nodes, then predicts each path's arrival time employing a Bayesian-based model capable of handling highly variable arrival time and generalizing to new designs. Experimental results on transfer learning from 130nm to 7nm nodes validate our method's effectiveness.
Event Type
Research Manuscript
TimeTuesday, June 2510:45am - 11:00am PDT
Location3008, 3rd Floor
EDA
Timing and Power Analysis and Optimization