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Presenter

Bei Yu
The Chinese University of Hong Kong
Presentations
Research Manuscript
WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Knowing The Spec to Explore The Design via Transformed Bayesian Optimization
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree
EDA
Physical Design and Verification
Research Manuscript
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration
AI
AI/ML Algorithms
Research Manuscript
Efficient ILT via Multigrid-Schwartz Method
Design
Design for Manufacturability and Reliability
Research Manuscript
PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry
EDA
Physical Design and Verification
Work-in-Progress Poster
An Effective Timing Driven Placement with Accurate Differentiable Timing Approximation Integration
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes
EDA
Timing and Power Analysis and Optimization
Research Manuscript
Fracturing-aware Curvilinear ILT via Circular E-beam Mask Writer
Design
Design for Manufacturability and Reliability
Research Manuscript
Efficient Bilevel Source Mask Optimization
Design
Design for Manufacturability and Reliability
Research Manuscript
Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation
EDA
Analog CAD, Simulation, Verification and Test
Research Manuscript
ChatPattern: Layout Pattern Customization via Natural Language
Design
Design for Manufacturability and Reliability
Research Manuscript
CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning
Design
Design for Manufacturability and Reliability
Research Manuscript
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
EMOGen: Enhancing Mask Optimization via Pattern Generation
Design
Design for Manufacturability and Reliability
Research Manuscript
NeuroSelect: Learning to Select Clauses in SAT Solvers
EDA
Design Verification and Validation
Research Manuscript
Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and Projection
EDA
Physical Design and Verification
Research Manuscript
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs
EDA
Physical Design and Verification