Presentation
A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems
DescriptionDomain-specific systems, consisting of custom hardware accelerators, improve the performance of a specific set of applications compared to general-purpose processing systems. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools often ignore the challenges of implementing a complex system of parallel accelerators, particularly regarding the way accelerators access memory. Our work proposes a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization on average by 53.2% for a set of PolyBench kernels.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
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Design
EDA
Embedded Systems
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Security