Presentation
ATAFAN: Design-Friendly Aging-aware Timing Analysis Framework Based on Hybrid Graph Network
DescriptionThe increasing prevalence of device aging significantly complicates the timing analysis of digital circuits, especially due to the time-consuming nature of current methodologies, which struggle with the variety of standard cells and diverse input conditions. Addressing this challenge, this work proposes a novel, design-friendly framework for efficient and rapid aging-aware timing analysis. This framework harnesses the capabilities of Hybrid Graph Neural Networks to effectively capture cell structural details and extract delay-related information, enabling a straightforward mapping from operational conditions to specific cell aging delays. Additionally, it incorporates a Relational Graph Convolution Network (R-GCN) for modelling the complex relationships between nodes and a Graph Attention Network (GAN) for assessing the relative importance of each node, based on their types. This integrated approach significantly streamlines the process of aging-aware timing analysis, offering a substantial improvement in both speed and accuracy for digital circuit design. Our framework has 5% to 28% higher average prediction accuracy and better generalization ability on new cell than other benchmark networks; Compared with the conventional method, our framework greatly reduces time consumption and achieve average acceleration ratio of 600 on prediction tasks of a large number of cell structures and input conditions.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security