Presentation
SI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner Consideration
DescriptionTiming closure is a critical but effort-taking task in VLSI designs. Early design stages have relatively ample room for changes that can fix timing problems in a proactive manner. However, accurate timing prediction is very challenging at early stages due to the absence of information determined by later stages in the design flow. At pre-routing stage, it is generally believed that the prediction of wire delay is more complicated than that of gate delay, since the former is highly dependent on the routing information and PVT conditions. Addressing that, in this work, prediction model is studied and the importance of multiple features are explored, with the purpose to boost the turn-around time of physical design and reduce the performance penalty caused by the worst-case scenario assumptions. Experimental results show that the proposed timing predictor has achieved a correlation over 0.98 with the Signal-Integrity (SI) sign-off timing results under multi-corner scenarios.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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