Presentation
How to Write RISC-V PSS Models to Enable Generating Verification Scenarios for RISC-V Platforms
DescriptionRISC-V is an industry wide ISA (Instruction Set Architecture) standard used for developing embedded processors that target Semiconductor products of any type. PSS (Portable Stimulus) is an Accellera standard verification language used by EDA companies to develop tools, that given a PSS Model, generates coverage driven scenarios to enable meeting verification goals with less effort, taking advantage of portability, abstraction, and automation capabilities enabled by the language. In this tutorial we teach how to code PSS Models needed for the verification of any RISC-V platform (e.g. RISC-V embedded core platform, RISC-V multi-core coherent platform, RISC-V SOC (System on Chip) with external interfaces, etc.).
Synopsys as a RISC-V developer is providing reference methodologies for the verification and debugging of RISC-V system designs are available now, along with Synopsys EDA flows, emulation and virtual prototyping solutions, and methodologies to further support RISC-V SoC verification. Collaborative efforts include RISC-V verification methodology cookbook for Bluespec cores, "Understanding UVM Coverage for RISC-V Processor Designs" white paper, RISC-V and processor verification using ImperasDV verification solutions, and the industry-leading Synopsys VCS® simulation and Verdi® debug tools for improved efficiency (see news release).
As PSS usage grows together with the incoming requests to better enable PSS for RISC-V platforms, we endeavor to expand on a methodology cookbook with the addition of PSS. In this tutorial we enable the RISC-V PSS eco community with some fresh ideas on how to use PSS to get started. We introduce the PSS modeling patterns below that can be used to get started and hopefully provide an appetite to use and create more.
For each modeling pattern, we give a name and a short explanation of what the pattern consists of:
(1) Basic: PSS modeling techniques that can be used to generate basic RISC-V assembly code sequences. (2) Integration: PSS modeling techniques that can be used to generate RISC-V assembly code that interacts with generated traffic scenario's consisting of embedded C and SV testbench generate code.(3) Nested loops and routines: PSS modeling techniques that can be used to generate legal assembly code with nested loops and nested routine calls.(4) Memory sharing: PSS modeling techniques that can be used to generate blocks of assembly code that share memory, with exclusive and non-exclusive access. (5) Runtime parameterization: PSS modeling techniques that can be used to generate parameterized assembly code run on a post-silicon, where a host device can change parameters on-the-fly.(6) Validating the scenario: PSS modeling techniques to create a reference model in PSS that can be used as an executable specification to debug and validate PSS generated scenarios.
The expectation is that this 3-hour tutorial will provide any RISC-V platform developer with a good enough tool kit to be able to perform all verification requirements needed for a RISC-V platform.
Synopsys as a RISC-V developer is providing reference methodologies for the verification and debugging of RISC-V system designs are available now, along with Synopsys EDA flows, emulation and virtual prototyping solutions, and methodologies to further support RISC-V SoC verification. Collaborative efforts include RISC-V verification methodology cookbook for Bluespec cores, "Understanding UVM Coverage for RISC-V Processor Designs" white paper, RISC-V and processor verification using ImperasDV verification solutions, and the industry-leading Synopsys VCS® simulation and Verdi® debug tools for improved efficiency (see news release).
As PSS usage grows together with the incoming requests to better enable PSS for RISC-V platforms, we endeavor to expand on a methodology cookbook with the addition of PSS. In this tutorial we enable the RISC-V PSS eco community with some fresh ideas on how to use PSS to get started. We introduce the PSS modeling patterns below that can be used to get started and hopefully provide an appetite to use and create more.
For each modeling pattern, we give a name and a short explanation of what the pattern consists of:
(1) Basic: PSS modeling techniques that can be used to generate basic RISC-V assembly code sequences. (2) Integration: PSS modeling techniques that can be used to generate RISC-V assembly code that interacts with generated traffic scenario's consisting of embedded C and SV testbench generate code.(3) Nested loops and routines: PSS modeling techniques that can be used to generate legal assembly code with nested loops and nested routine calls.(4) Memory sharing: PSS modeling techniques that can be used to generate blocks of assembly code that share memory, with exclusive and non-exclusive access. (5) Runtime parameterization: PSS modeling techniques that can be used to generate parameterized assembly code run on a post-silicon, where a host device can change parameters on-the-fly.(6) Validating the scenario: PSS modeling techniques to create a reference model in PSS that can be used as an executable specification to debug and validate PSS generated scenarios.
The expectation is that this 3-hour tutorial will provide any RISC-V platform developer with a good enough tool kit to be able to perform all verification requirements needed for a RISC-V platform.
Event Type
Tutorial
TimeMonday, June 241:30pm - 5:00pm PDT
Location3001, 3rd Floor
EDA