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Organization

Synopsys
Contributors
Kartik Agarwal
Deepak Ahuja
Rob Aitken
Jaskaran Ajimal
James Ban
Sachin Bansal
suresh barla
Vikram Bhatia
Aashish Bhide
Vuk Borich
Mike Borza
Sanjeev Chaudhri
Navneet Chaurasia
Hari Cherupalli
Rimpy Chugh
Joe Cole
Sabya Das
Kamal Desai
Kamal Desai
Mallik Devulapalli
Stelois Diamantidis
Li Ding
Neelabja Dutta
Sassine Ghazi
Manish Goel
Priyanka Goel
Amit Goldie
Sanjay Gulati
Avinash Gupta
Nupur Gupta
Sangwoo Han
Patrick Haspel
Sunik Heo
Ho-Chieh Hsu
Yinghua Hu
Angela Hwang
Reily Jacoby
PARAS MAL JAIN
Priyanshi Jain
Praveen Jakki
Amit Jalota
Luna Kang
Ashish Kapoor
Himanshu Kathuria
Jamil Kawa
Anish Keshava
Vishal Keswani
Ann-Woo Lee
I-Te Lin
Chia-Ming Liu
Yi Liu
Pawini Mahajan
Gunjan Mamania
Sandeep Mehrotra
Hillel Miller
Anurag Mittal
Aakarshak Nandwani
Sashi Obilisetty
Sridhar Panchapakesan
Ganapathy Parthasarathy
Satyanarayana Patnala
Vijay Poosa
Gaurav Pratap
M.Vaishnavi Reddy
Nitesh S
Sridharr S
Jayson Seo
Nitin Sharma
Vartul Sharma
Ahmed Shebaita
Rakesh Shenoy
Rakesh Shenoy
Deepak Sherlekar
Tajendra Singh
Harsha Somashekar
Fengfeng Tang
Peivand Tehrani
Kenneth Trejos
Vivek Uppal
Santosh Varanasi
Jin Wang
Ameer Youssef
Yervant Zorian
Session Chairs
Maheshwar Chandrasekar
Parivesh Choudhary
Jon Colburn
Sabya Das
Yinghua Hu
Igor Markov
Presentations
Research Panel
3DIC Design Ecosystem – The Cats That Need Herding!
Design
Engineering Track Poster
A Solution for Optimizing Customerized-MMB
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Advanced LLE aware Timing Signoff Methodology
Back-End Design
Embedded Systems
Front-End Design
IP
Exhibitor Forum
Architecting a True Hybrid Cloud Environment for Massively Parallelized EDA Workloads
Engineering Track Poster
Automated Constraint Promotion Methodology from IP to SoC for Complex Designs
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Automated Design Scenario Extraction From A Large Design For Faster Debug Of Static Verification Tools
Engineering Tracks
IP
Engineering Track Poster
Avoiding CDC bugs introduced during Synthesis Optimizations and Netlist Transformations
Back-End Design
Embedded Systems
Front-End Design
IP
DAC Pavilion Panel
Best of Both Worlds: Bridging the Gaps in Engineering Software for Semiconductors and Systems
Front-End Design
Breaking the Formal Convergence Barriers of a Floating-Point Dot-Product Block for AI/ML Accelerators
Design
Engineering Tracks
Front-End Design
IP
CDC Multimode Signoff Methodology
Engineering Tracks
IP
IP
Considering Selective Resistance Extraction for Performance & Accuracy Trade-off for Memory IP Simulation
Engineering Tracks
IP
Engineering Track Poster
Dashboard Model for Foundry Early Node Assessments using Synopsys Design.da
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Democratizing Chip Design
Engineering Tracks
IP
IP
Demystifying Failure Mechanisms at Advanced Nodes
Engineering Tracks
IP
Back-End Design
Design Automation Advancement in the Analog Domain
Back-End Design
Design
Engineering Tracks
Front-End Design
Design Constraint Strategy For Dealing With Cascaded Clock MUX Structures
AI
Design
Engineering Tracks
Front-End Design
IP
Enabling Protocol Validation of High Speed Serial Links using SerDes to transfer data between PHY Chip and Link layer on FPGA
Engineering Tracks
IP
IP
Fast and Deterministic Memory Yield Estimation Using Machine Learning Augmented Statistical Simulations
Engineering Tracks
IP
Research Panel
Generative AI for Chip Design: Game Changer or Damp Squib?
AI
EDA
IP
Going Vertical. Challenges of the Automotive Silicon Ecosystem
Engineering Tracks
IP
Engineering Track Poster
Heterogeneous 3DIC Multi Voltage Timing Signoff
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
History, Present, and Future of STA: A Travel Through Timing
Back-End Design
Design
Engineering Tracks
Tutorial
How to Write RISC-V PSS Models to Enable Generating Verification Scenarios for RISC-V Platforms
EDA
Special Session (Research)
Invited: HDL-GPT: High Quality HDL Is All You Need
AI
Late Breaking Results Poster
Late Breaking Results: On the One-Key Premise of Logic Locking
IP
NoC NoC – Who's There?
Engineering Tracks
IP
Research Panel
Power Your Future: Investments for the Chip Design Workforce and Research
EDA
Engineering Track Poster
Programmable IO Ring Builder and checker
Back-End Design
Embedded Systems
Front-End Design
IP
Research Panel
Quantum Computing: Accomplishments, Bottlenecks, and Timelines
Design
Quantum Computing
Front-End Design
Shift Left Detection and Root Cause Analysis of Synthesis Optimized Registers at RTL Level
AI
Design
Engineering Tracks
Front-End Design
Engineering Track Poster
Shift-left Solution for Enhancing Power Integrity in physical design construction with RedHawk-Fusion
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Virtual Instrumentation Based Predictive Checks for Shift-Left Low Power Verification
Back-End Design
Embedded Systems
Front-End Design
IP
Research Manuscript
Voronoi Diagram-based Multiple Power Plane Generation on Redistribution Layers in 3D ICs
EDA
Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package
Sessions
Research Manuscript
Advanced in Silicon Lifecycle Management & Test
EDA
Test, Validation and Silicon Lifecycle Management
Research Manuscript
The Next Step to Efficient AI: Number Formats, Quantization and Beyond
AI
AI/ML Algorithms
Research Manuscript
Advanced Logic Synthesis - Improving Runtime and Quality
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
Learn and Fuzz!
EDA
Design Verification and Validation
Research Manuscript
AI Paradigms beyond Deep Neural Networks
AI
AI/ML Algorithms
Research Manuscript
Attacks and Defenses at Microarchitecture Level and Beyond
Security
Hardware Security: Primitives, Architecture, Design & Test