Presentation
GREAT: Gen-AI Research in Electronic Design, Automation, and Test
DescriptionLarge language models (LLMs) have been a significant breakthrough in artificial intelligence, demonstrating remarkable success in solving various real-world problems. These models, trained on vast amounts of text data, have shown an uncanny ability to generate human-like text, understand context, answer questions, and write code. They have been successfully deployed in numerous applications, including customer service, content creation, and language translation, to name a few. The versatility and robustness of LLMs have made them an invaluable tool in the AI toolkit, opening up avenues for exploration and innovation. Microsoft, Google, Meta, and Amazon have invested in generative AI technologies like LLMs.
One such avenue that has garnered attention is using LLMs in chip design. Digital chip design, a complex and intricate process, involves the creation of integrated circuits used in various electronic devices. LLMs are expected to aid designers during design and concept development, verification, validation, and security checks. For instance, Synopsys has recently developed an LLM-based framework to aid chip design and development.
With these revolutionary developments and interest from leading electronic design automation companies (Cadence, Synopsys, Siemens) and chip design companies (Intel, Nvidia, Qualcomm, IBM, etc.), there is an increasing need for a greater understanding of LLMs' roles in EDA. We will organize the first "Workshop on Gen-AI for Chip Design." This workshop will comprise three types of knowledge sharing:
(i) Two-hour session on visionary talks from industry and government leaders (10:00-Noon),
(ii) Two-hour lunch poster session from academic/industry researchers (Noon-2:00).
(iii) Two-hour prompt engineering tutorial/competition (e.g., RTL generation) open to the EDA, AI, and Design community (students, academics, practitioners, hobbyists) (2:00-4:00).
(iv) One-hour closing session on the next steps.
Together, these sessions will highlight the trends and needs in industry, research adventures in academia, and bridge the gap between the two.
One such avenue that has garnered attention is using LLMs in chip design. Digital chip design, a complex and intricate process, involves the creation of integrated circuits used in various electronic devices. LLMs are expected to aid designers during design and concept development, verification, validation, and security checks. For instance, Synopsys has recently developed an LLM-based framework to aid chip design and development.
With these revolutionary developments and interest from leading electronic design automation companies (Cadence, Synopsys, Siemens) and chip design companies (Intel, Nvidia, Qualcomm, IBM, etc.), there is an increasing need for a greater understanding of LLMs' roles in EDA. We will organize the first "Workshop on Gen-AI for Chip Design." This workshop will comprise three types of knowledge sharing:
(i) Two-hour session on visionary talks from industry and government leaders (10:00-Noon),
(ii) Two-hour lunch poster session from academic/industry researchers (Noon-2:00).
(iii) Two-hour prompt engineering tutorial/competition (e.g., RTL generation) open to the EDA, AI, and Design community (students, academics, practitioners, hobbyists) (2:00-4:00).
(iv) One-hour closing session on the next steps.
Together, these sessions will highlight the trends and needs in industry, research adventures in academia, and bridge the gap between the two.
Event Type
Workshop
TimeSunday, June 231:00pm - 5:00pm PDT
Location3004, 3rd Floor
AI