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Organization

Huawei
Contributors
Renzo Andri
Kai-Yuan Chao
Lei Chen
Aiguo Cui
Aritra Dhar
Bentian Jiang
Shixiong Kai
Xing Li
Weihua Sheng
xiong silu
Yang Tao
Dimitrios Tsaras
Siyuan Xu
Lihao Yin
Mingxuan Yuan
Xing Zhang
Hui-Ling Zhen
Presentations
Research Manuscript
CFTCG: Test Case Generation for Simulink Model through Code Based Fuzzing
EDA
Design Verification and Validation
Work-in-Progress Poster
Circuit Transformer: End-to-end Logic Synthesis by Predicting the Next Gate
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Work-in-Progress Poster
Confidential Computing with Heterogeneous Devices at Cloud-Scale
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
Efficient Code Generation for Data-Intensive Simulink Models via Redundancy Elimination
Embedded Systems
Embedded Software
Work-in-Progress Poster
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Work-in-Progress Poster
Escaping local optima in global placement
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis
EDA
Timing and Power Analysis and Optimization
Research Manuscript
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs
EDA
Physical Design and Verification
Research Manuscript
NeuroSelect: Learning to Select Clauses in SAT Solvers
EDA
Design Verification and Validation
Research Manuscript
Obstacle-Aware Length-Matching Routing for Any-Direction Traces in Printed Circuit Board
EDA
Physical Design and Verification
Work-in-Progress Poster
Principles for Enabling TEEs on Domain-Specific Accelerators
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
Size-Optimized Depth-Constrained Large Parallel Prefix Circuits
EDA
RTL/Logic Level and High-level Synthesis