Presentation
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs
DescriptionNon-integer multiple cell height (NIMCH) standard-cell libraries offer promising co-optimization for power, performance and area in advanced technology nodes. However, such non-uniform design introduces new layout constraints where any sub-region can only accommodate gates of the same cell height. The existing physical design flow for NIMCH circuits handles the constraint by clustering and relocating gates according to their cell heights, inevitably causing displacement that harms circuit performance. This paper proposes a placement-aware logic resynthesis procedure that explicitly adjusts cell heights after initial placement without changing cell location. Experiment results demonstrate that our approach can reduce the maximal delay by 26.1%.
Event Type
Research Manuscript
TimeThursday, June 272:45pm - 3:00pm PDT
Location3004, 3rd Floor
EDA
Physical Design and Verification