Presentation
UCIe-A 32GT/s power distributed network design-optimization at organic interposer with localized integrated passive decoupling capacitors
DescriptionThis paper presents a power distributed networks (PDNs) design for UCIe-A (UCIe advanced package), at organic interposer technology. To meet UCIe-A power integrity requirement for voltage fluctuation (Vpp) less than 30mV, interposer level decoupling capacitors is a critical design (e.g., distributed eDTC at CoWoS-S). However, at organic inteposer, it is still limited solution for localized and efficiently noises decoupling, especially, UCIe-A X64E bump map IP hardmarco is with small dimension as 1225μm x 388.8μm.
This work proposes a localized decoupling capacitor integrated solution, deploying C4-bump-side integrated passive components (IPDs) at UCIe-A X64E die-to-die gap, which provides efficiently local decoupling paths for each UCIe-A IP macro, as well as without penalty of PDNs parasitics degraded or occupied extra region for decoupling capacitors.
This work demonstrates the design of UCIe-A X64E testchip in tsmc 3nm technology (tape out on 2023/Nov.), as well as interconnects and PDNs at tsmc 65nm organic interposer (CoWoS-R, 8-RDL), where the PDNs co-simulated peak impedance (ZPDN) can be suppressed by 55% (from 21.59mΩ to 11.87mΩ, at 100MHz), as well as peak-to-peak voltage fluctuation (Vpp) can be suppressed by 78.7% (from 103.00mV to 21.98mV). With the good PDNs design, related power-aware SI co-simulated eyediagram can achieve 0.78UI at 32GT/s.
This work proposes a localized decoupling capacitor integrated solution, deploying C4-bump-side integrated passive components (IPDs) at UCIe-A X64E die-to-die gap, which provides efficiently local decoupling paths for each UCIe-A IP macro, as well as without penalty of PDNs parasitics degraded or occupied extra region for decoupling capacitors.
This work demonstrates the design of UCIe-A X64E testchip in tsmc 3nm technology (tape out on 2023/Nov.), as well as interconnects and PDNs at tsmc 65nm organic interposer (CoWoS-R, 8-RDL), where the PDNs co-simulated peak impedance (ZPDN) can be suppressed by 55% (from 21.59mΩ to 11.87mΩ, at 100MHz), as well as peak-to-peak voltage fluctuation (Vpp) can be suppressed by 78.7% (from 103.00mV to 21.98mV). With the good PDNs design, related power-aware SI co-simulated eyediagram can achieve 0.78UI at 32GT/s.
Event Type
Back-End Design
TimeWednesday, June 2610:30am - 10:48am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks