Presentation
Die, Package and PCB Co-design for Low Area, High Signal to Power Pin Ratio in High Frequency SOC designs
DescriptionØ Microcontroller designs are going through optimizations on multiple-scales to win market share – be it performance, MIPS, feature-set, more peripheral access, more systems on chip supporting more applications.
Ø Simultaneous support of varied applications and win customers mandate availability of higher count of pins/GPIOs as compared to predecessors/competitors – which indirectly means sacrificing the count of power/ground pins.
Ø For our design, we have set target of power-pins reduction by 40% on Core and IO power supplies, thereby providing more pins for GPIOs. Along with this, there was increase in supply tolerance.
Ø Reduced count of power/ground pins, increased functionality, higher supply tolerance on IO supply have negative impacts on IR drop, timing, Signal Integrity (SI), and hence overall design performance.
Ø Industrial solutions like PTV compensation circuits, programmable drive cells would solve the problem for SI, however, they bring higher area overhead.
Ø Through this paper we present cost-effective (area) design strategies that were incorporated to keep all the above design vectors in reasonable limits without area penalties. We will showcase the signal-integrity aspects wrt GPIO pads and see how they were addressed.
Ø Simultaneous support of varied applications and win customers mandate availability of higher count of pins/GPIOs as compared to predecessors/competitors – which indirectly means sacrificing the count of power/ground pins.
Ø For our design, we have set target of power-pins reduction by 40% on Core and IO power supplies, thereby providing more pins for GPIOs. Along with this, there was increase in supply tolerance.
Ø Reduced count of power/ground pins, increased functionality, higher supply tolerance on IO supply have negative impacts on IR drop, timing, Signal Integrity (SI), and hence overall design performance.
Ø Industrial solutions like PTV compensation circuits, programmable drive cells would solve the problem for SI, however, they bring higher area overhead.
Ø Through this paper we present cost-effective (area) design strategies that were incorporated to keep all the above design vectors in reasonable limits without area penalties. We will showcase the signal-integrity aspects wrt GPIO pads and see how they were addressed.
Event Type
Back-End Design
TimeWednesday, June 2610:48am - 11:06am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks