Presentation
Memory IO Block Routing Optimization using Semi-Automation of Single Trunk Steiner Tree Routing
DescriptionIn memory products, IO blocks for data interfaces have been using a custom-based design methodology. We use pre-layout simulation to predict chip performance in the early stage of schematic design using Steiner tree-based routing estimation. Based on the simulation results, we place and fix standard cells and macros, and then perform routing. For critical nets, we manually route the nets in the form of Steiner trees and auto route the rest of the nets automatically
However, the existing design methodology is facing limitations in terms of routability and turn-around time due to the increase of routing constraints with continuous rise in IO speed and the reduction of routing tracks due to area optimization.
In this work, we propose the following methods:
1. We develop a semi-automated router to generate a single-trunk Steiner tree considering basic design rules
2. We improve the routability of critical nets by combining the semi-automated router with the auto-router of the P&R tool
3. We minimize parasitic RC overhead by optimizing wire spacing and layers
We applied proposed methodology to a flash design and observed significant improvements in physical DRC violations and design turn-around time while maintaining layout expert's manual routing quality.
However, the existing design methodology is facing limitations in terms of routability and turn-around time due to the increase of routing constraints with continuous rise in IO speed and the reduction of routing tracks due to area optimization.
In this work, we propose the following methods:
1. We develop a semi-automated router to generate a single-trunk Steiner tree considering basic design rules
2. We improve the routability of critical nets by combining the semi-automated router with the auto-router of the P&R tool
3. We minimize parasitic RC overhead by optimizing wire spacing and layers
We applied proposed methodology to a flash design and observed significant improvements in physical DRC violations and design turn-around time while maintaining layout expert's manual routing quality.
Event Type
Back-End Design
TimeMonday, June 241:48pm - 2:06pm PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks