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Organization

Samsung
Contributors
choudhary Aditya Kumar
Seyong Ahn
CheolJun Bae
Heejin Bae
Sougata Bhattacharjee
Arpan Bhowmik
Sungsu Byun
Seongpil Chang
Abhishek Mahesh Chinchani
Venkata Chinni
kyoungsun cho
HONGSEOK CHOI
Hyojin Choi
Jung Yun Choi
Sekhar Dangudubiyyam
Lukasz Dudziak
Hongxiang Fan
Seungik Ha
Sangwoo Han
Seungkwang Hong
Yongjin Hong
Bosun Hwang
Jaewoo Im
Sandeep Jadhav
Sandeep Jadhav
Jaeyeong Jeon
Kwangok Jeong
Hyunmi Ji
Kyeongrok Jo
Youngjin Ju
Euibong Jung
Jongyoon Jung
Kiwook Jung
Minho Jung
Seungjae Jung
Keerthana K
Dongku Kang
Jongkoo kang
Kwonchil Kang
Kyungsu Kang
Seoklip Ki
Ahreum Kim
CHANGWON KIM
Daeyeon Kim
Dongjin Kim
Doyun Kim
Hyejin Kim
Hyeyoun Kim
Hyojin Kim
Jinbeom Kim
Jung-Hoon Kim
jungho kim
Ki-Ok Kim
Kwangsun Kim
Kwonjae Kim
Minkook Kim
Minkyung Kim
Myeongjin Kim
Sangyun Kim
Seyoung Kim
Sichan Kim
Sua Kim
Suhwan Kim
sunghoon kim
wonchol kim
wook kim
Yoobeom Kim
Youngwook Kim
Bonhyuck Koo
Vijay Kumar
Pansuk Kwak
Ohhun Kwon
SRUTI L SHRIDHAR
Celeste Anil Lagali
Boyoung Lee
Byunghyun Lee
Daehee Lee
Dongyoung Lee
Hyein Lee
Jeongyoon Lee
Jingon Lee
Jiseon Lee
Jooseong Lee
Mintae Lee
Se-Hoon Lee
Seunghwan Lee
Sunghee Lee
Taehyung Lee
Woonggyu Lee
Yongseok Lee
Yoon Hyeok Lee
Youngchan Lee
Yunseong LEE
Amresh Lenka
Heejae Lim
Junhee Lim
Mijeong Lim
Tadasa Mahapatra
Lalithraj Mailappa
Rishikanth Mekala
Arvind Kumar Mishra
Tusharkant Mishra
Kiyoung Moon
Seyeon Moon
Seongjin Mun
Daeun Oh
Youngmin Oh
Dhaval Panchal
Jaemin Park
Jihoon Park
Jongseong Park
Peter Park
Songyi Park
Sungho Park
SUNGSIK PARK
Younsik Park
Subramanian R
Raja Rama Chandra Rao
Chul Rim
Soonkeol Ryu
Hyun-seung Seo
Hyungjung Seo
Hyunseung Seo
Hyunseung Seo
Jun Seomun
Gulshan Sharma
Changyoon Shin
Dongseok Shin
Seongkyun Shin
Jichang Sim
Jaeyoung So
Goda Ananth Somayaji
Naveen Srivastava
Naveen Srivastava
Damodaran Trikkadeeri
Sowmya V M
Ranjith V R
Jooho Wang
Choi Wonwoo
Jiwon Woo
Yoojeong Yang
Jimin Yeo
Dongsub Yoon
Changyeon Yu
Presentations
Engineering Track Poster
3DIC prototype design and transient early thermal analysis
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
A Data-Driven Automation Method of Liberty Model Characterization for Custom Cells
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
A Heuristic-Based Routing Methodology for Block-Level Memory Layout Routability Enhancement
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
A module based automation for AXI performance monitoring, performance extraction and protocol checking.
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
A Novel Solution for Fast and Efficient Custom Bus Routing with User-defined Reference Wire and Combination of Segmented Bus Option
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Advanced LLE aware Timing Signoff Methodology
Back-End Design
Embedded Systems
Front-End Design
IP
IP
AI-based High Sigma Verification Methodology for Multiple PVT Corners
Engineering Tracks
IP
Engineering Track Poster
An Automated Solution for Streamlining Qualifications of Connectivity and DRC Across Diverse 3DIC Packaging Technologies
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Auto Grouping And Improvement Of IR Critical Regions Using Unsupervised Learning
Back-End Design
Embedded Systems
Front-End Design
IP
Embedded Systems and Software
Automated Generation of SSD Stress Tests Using Offline Reinforcement Learning
AI
Embedded Systems
Engineering Tracks
Engineering Track Poster
Bus Delay Skew Minimization for High Bandwidth Memory Designs
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Calibre Autowaiver for Early DRC & DFM Analysis In Big Die Designs
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
CDC Simulation Checker Implementation for Constant and Quasi-static Data Paths
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
COBRA : Code Coverage Measurement Technique for ARM-based firmware using Binary Modification Technology
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Design Methodologies for Minimizing Local Routing Congestions in Low-level Metal Layers
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Development of SystemC-based Security VP for In-House SED SSD Firmware Verification and Application of libFuzzer
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
DVD-aware STA and its silicon correlation results on 10nm test chip
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Early Validation of Random TB using Formal Technology
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Flash-based storage systems exploiting the data period for performance and security enhancement
Back-End Design
Embedded Systems
Front-End Design
IP
Embedded Systems and Software
Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
AI
Embedded Systems
Engineering Tracks
Engineering Track Poster
Globalized bulk biasing based substrate noise reducing method for size reduction in digital circuit
Back-End Design
Embedded Systems
Front-End Design
IP
Research Manuscript
Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Engineering Track Poster
Heterogeneous 3DIC Multi Voltage Timing Signoff
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
High Coverage QA for Process Variability Compensation in LVS Rule Deck
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Holistic Approach on 3DIC Planning
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Leveraging several automated techniques and methodologies for faster coverage closure and design sign-off
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Machine Learning Optimization Switch cells.
Back-End Design
Embedded Systems
Front-End Design
IP
Work-in-Progress Poster
MACO: Model-based Adaptive Circuit Optimization by Transformer-based Bidirectional Predictions between Circuit Parameters and Specifications
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Back-End Design
Memory IO Block Routing Optimization using Semi-Automation of Single Trunk Steiner Tree Routing
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Methodology of linking the LDR and DRC code by automatically generated test pattern
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
ML based PPA Push using DRV Prediction
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Parasitic Leakage Detection in Layout Design
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Plug-n-Play Testbench environment for ARM Coresight SoC-400
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Pnr implementation challenges in 3d ic
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
RDL and Bump Automation for Early EMIR Analysis In 2.5D, 3D and Single DIE Designs using RedHawk-SC Design ECO's
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Reducing Interlayer misalignment caused by BLE (Bulk Layout Effect) : Solutions for improving in-chip uniformity of alignment between two layers
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Samsung's IP QA methodology using Solido Crosscheck
Engineering Tracks
IP
Engineering Track Poster
Struct Based Lower Level Modelling Using SystemVerilog UDT for Verification of Power Management IC
Back-End Design
Embedded Systems
Front-End Design
IP
Research Manuscript
TraceFormer: S-parameter Prediction Framework for PCB Traces based on Graph Transformer
EDA
Analog CAD, Simulation, Verification and Test
Back-End Design
TSV KOZ separation 3DIC P&R area optimization methodology considering device impact by TSV
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Unified Waveform Analysis Platform for Tr.-Level Design Verification
Back-End Design
Embedded Systems
Front-End Design
IP