Close

Presentation

Si Backside Side-Channel Leakage and Simulation of Cryptographic IC Chips
DescriptionFlip chip mounting has been widely used in recent years. Flip chip mounting has advantages such as shorter signal wires, smaller footprint, and multiple chip(lets).
However, flip chip packaging makes Si substrate as an attack surface, and then Si substrate voltage becomes one of the side-channel information.
Therefore, we develop analysis flow of Si substrate voltage using Chip Power Model (CPM). CPM is made of power library of standard cells, logic transition of digital circuit, design data. In order to analyze an accurate Si substrate voltage, design data information that is required to create CPM includes Si substrate configuration, thickness, resistance, capacitance.CPM is created for each dataset with changing input vectors for side-channel leakage evaluation.
We confirm that side-channel attack is successful using waveforms from CPM.
Furthermore, we find the possibility of localized and chip thickness dependent noise propagation by analyzing of waveforms from CPM. As for locality, we also confirmed that the matching between measurement and simulation.
Event Type
Back-End Design
TimeWednesday, June 2611:06am - 11:24am PDT
Location2008, 2nd Floor
Topics
Back-End Design
Design
Engineering Tracks