Presentation
Reducing Test Dynamic IR and Vmin for Automotive and Industrial Radar SoCs using Power Aware DFT Methodology
DescriptionAutomotive radar sensors are mounted at the edges of the vehicle, where ambient temperatures of up to 85C need to be supported and providing good cooling solutions adds heavily to the sensor cost. With growing number of radar sensors per vehicle and the entry to radar sensors in the low/mid segment cars, there is a huge pressure on the radar sensor cost from the OEMs. By reducing the VDD supply by 4.5% , the leakage active current of the chip reduces by ~10%. This reduces the complexity and size of the heat sinking solution on the sensor and hence reduces the heat sink cost at the sensor. Therefore, in automotive radar sensors, one of the major power objectives is to reduce the Vmin of the device to reduce the overall power consumption. For industrial radar sensors, focus is more on the leakage current reduction as the device would be operating on battery and low deep sleep current would be required for minimized energy consumption and prolonged battery life.
The power consumption of a chip is directly proportional to its switching. The typical behavior of ATPG and MBIST engine is to target as many faults as possible with as little patterns as possible. This increases the switching activity of the test patterns and hence the power requirement for ATPG tends to be significantly higher than functional operation. Testing at reduced Vmin is required to distinguish between functionally correct devices and devices that are defective due to Vmin issues and production abnormalities. However, Vmin reduction is an iterative process between Product Engineering (PE) team and DFT team, taking more than one month to close. This paper proposes comprehensive power aware DFT methodology for reducing the overall Vmin of Scan and MBIST patterns to enable digital supply reduction without compromising on yield or test data volume (TDV) and the proposed methodology aims to reduce the turnaround time to generate power efficient patterns.
The power consumption of a chip is directly proportional to its switching. The typical behavior of ATPG and MBIST engine is to target as many faults as possible with as little patterns as possible. This increases the switching activity of the test patterns and hence the power requirement for ATPG tends to be significantly higher than functional operation. Testing at reduced Vmin is required to distinguish between functionally correct devices and devices that are defective due to Vmin issues and production abnormalities. However, Vmin reduction is an iterative process between Product Engineering (PE) team and DFT team, taking more than one month to close. This paper proposes comprehensive power aware DFT methodology for reducing the overall Vmin of Scan and MBIST patterns to enable digital supply reduction without compromising on yield or test data volume (TDV) and the proposed methodology aims to reduce the turnaround time to generate power efficient patterns.
Event Type
Back-End Design
TimeTuesday, June 2511:24am - 11:42am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks