Presentation
Pruning Netlist: A Smarter Approach to Efficient and Reliable Circuit Characterization
DescriptionThis Presentation explores the challenges of IO cell design and its accurate characterization in the rapidly evolving field of chip design, where the demand for reducing chip size and increasing design functionalities has become more complex and fast-paced. To overcome these challenges an improvised design approach that customizes the last-stage flip-flop of the controller and implements it in the periphery IO architecture, resulting in decreased clock-to-data turnaround time. To overcome the characterization challenges for customized design, the paper proposes a pruning netlist technique that improves run time and accurate constraint values extraction in characterization. The results demonstrate the effectiveness of the proposed approach in overcoming the conventional characterization approach in terms of run time and accuracy.
Event Type
Back-End Design
TimeMonday, June 2411:10am - 11:25am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks