Session
Explore Concepts of STA Thru Insightful Craftsmanship
DescriptionExplore how you drive STA through 3D to ML techniques or simply closing timing on large designs be it through pruning margins, multiple clock sources or just partitioning effectively.
Event TypeBack-End Design
TimeMonday, June 2410:25am - 11:55am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks
Presentations
| 10:25am - 10:40am PDT | TSV KOZ separation 3DIC P&R area optimization methodology considering device impact by TSV | |
| 10:40am - 10:55am PDT | ML based PPA Push using DRV Prediction | |
| 10:55am - 11:10am PDT | Model Margining Algorithm for High Performance SOC closure | |
| 11:10am - 11:25am PDT | Pruning Netlist: A Smarter Approach to Efficient and Reliable Circuit Characterization | |
| 11:25am - 11:40am PDT | Clock parameter tuning with an intelligent adaptive learning to improve performance and power of Multisource Clock Tree Synthesis | |
| 11:40am - 11:55am PDT | An effective Hierarchical STA solution for closing Large SoC Design |