Presentation
System Aware IO Integrity Signoff
DescriptionIO integrity analysis early in the design cycle helps disintegrate the system level constraints from DIE level constraint. Integrity challenges are more predominant with 324-529 BALL packages, in automotive infotainment SOCs with close to 200-400 signals including GHz DDR, EMAC, eMMC, xSPI etc. Total power being supported ranging up to 10Watts.
This paper discusses System aware IO integrity analysis which enables faster engagement closure among design, test, and application/customer.
This paper discusses System aware IO integrity analysis which enables faster engagement closure among design, test, and application/customer.
Event Type
Back-End Design
TimeWednesday, June 2611:24am - 11:42am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks