Presentation
Transforming Semiconductor Designs using SystemC based Shift-Left methodologies
DescriptionSince the inception of the semiconductor industry in the 1950s, there have been continuous advancements on multiple fronts. Semiconductor chips are becoming more and more powerful & complex.
Designing such complex chips is extremely difficult, costly and error prone. Design methodologies have also evolved to keep the pace with growing complexity. Historically this evolution came in the form of raising the abstraction of chip design: component level to gate level, and further to RTL.
Shift-left methodology allows the identification and resolution of flaws early in the design cycle. Fast simulation models allow early software development in parallel to hardware design. It is feasible to engage with the potential customers and validate the SoC architecture with the real customer workloads quite early in the cycle. These methodologies significantly reduce the Cost & Time to market. Overall it enhances the probability of success for a new SoC.
Two key trends in the industry today are, usage of chips for AI applications, and emergence of an open source processor architecture RISC-V ISA. Effective use of the ESL methodologies is necessary for the success of these trends.
The presentation will cover the virtual prototype of Core-V-MCU, an open source System on Chip from OpenHW group. This SoC has a RISC-V CPU core, an embedded FPGA, on chip SRAM, and a rich set of peripherals.
Designing such complex chips is extremely difficult, costly and error prone. Design methodologies have also evolved to keep the pace with growing complexity. Historically this evolution came in the form of raising the abstraction of chip design: component level to gate level, and further to RTL.
Shift-left methodology allows the identification and resolution of flaws early in the design cycle. Fast simulation models allow early software development in parallel to hardware design. It is feasible to engage with the potential customers and validate the SoC architecture with the real customer workloads quite early in the cycle. These methodologies significantly reduce the Cost & Time to market. Overall it enhances the probability of success for a new SoC.
Two key trends in the industry today are, usage of chips for AI applications, and emergence of an open source processor architecture RISC-V ISA. Effective use of the ESL methodologies is necessary for the success of these trends.
The presentation will cover the virtual prototype of Core-V-MCU, an open source System on Chip from OpenHW group. This SoC has a RISC-V CPU core, an embedded FPGA, on chip SRAM, and a rich set of peripherals.
Event Type
Exhibitor Forum
TimeMonday, June 243:30pm - 4:00pm PDT
LocationExhibitor Forum, Level 1 Exhibit Hall