Presentation
Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
DescriptionIn conventional embedded SoC development, SW development schedule is determined by HW prototype (e.g., FPGA). The SW development based on virtual platform (VP) has been used in industrial filed. This presentation describes how to apply the IP model provided by the 3rd party to the in-house VP for improving functional accuracy of in-house VP. The proposed method supports shared memory-based IPC to synchronize between the two model's simulations. It also translates data format from application-specific I/F (VP-side) into SystemC-TLM I/F (EDA IP-side), and vice-versa. The experimental results show that the functional accuracy increases up to 100% with only a small fraction (i.e., 8%) of the simulation time increase. The proposed work helps not only for shift-left of SW development, but also for improving SW quality through VP-based CI/CD because of the improvement of functional accuracy.
Event Type
Embedded Systems and Software
TimeWednesday, June 261:48pm - 2:06pm PDT
Location2010, 2nd Floor
AI
Embedded Systems
Engineering Tracks