Presentation
Smart Testing: Integrating Fault Simulation and AI/ML for Efficient IP Validation
DescriptionIn this innovative approach to IP validation, we address growing complexity of designs by integrating advanced Fault Simulation (FS) and Artificial Intelligence/Machine Learning (AI/ML) techniques. Traditionally, validating (I/O) in complex IP designs required extensive test vectors, leading prolonged simulation times. Recognizing these challenges, we propose paradigm shift, leveraging AI/ML-generated models to streamline processes. The implementation flow begins with fault list generation using Python Scripts through IP design simulation and creating test vectors for identified signals. These vectors, including GM and FM stimuli and simulation runs, and then processed through an AI/ML tool, Colab, resulting in the development of a robust model using 20% test vectors. The model validated against the 80% test vectors for max accuracy between Predicted & Actual. Application of model to the next run of IP design simulation on 20% Test Vectors ensures prediction of the 80% results. Notably, fault simulation with the reduced test vector set markedly decreases simulation time. Our methodology brings forth efficiency gains in I/F validation, offering continuous and reliable processes adaptable to design iterations. Through this integration of AI/ML and FS, we present comprehensive solution that not only optimizes testing efficiency but also ensures robustness in validating modern, intricate IP designs.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP