Presentation
Timing Closure Methods on 5nm Design Challenges
DescriptionHold timing violations can be challenging to fix especially with additional limitations in a 5nm design that were not seen in larger nodes, such as power, crosstalk, and narrower setup-hold window (less setup margin). Current Place and Route (PnR) and timing eco tools struggle to address these difficult hold violations due to the use of limited timing views for acceptable runtime and the tendency to insert excess hold padding that may have issues with wiring and power. This presentation describes four methods that can reduce hold violations with a less impact on power and wiring resources. The methods are: Reducing the VT on the existing cells, reducing the drive strength on existing cells, placing delay cells further away that is less congested and with wiring resources, and manipulating the clock so there would be less hold violations due to a wide clock skew. These methods provide additional solutions besides the traditional padding method so that the timing closure is not deadlocked with power and wiring issues.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP