Presentation
Early detection of low power related issues using formal verification
DescriptionLow Power design is now required to satisfy the current global market request in reducing ASIC power consumption. Incorrect power aware description can compromise the original design functional behavior, such as the propagation of corrupted signals due to an incorrect isolation control signals protocol. Low Power structural checks ensure that the design is structurally safe but do not guarantee functional correctness. Low Power functional simulations highly depend on simulation scenarios, which may result in non-exhaustive verification in case of a lack of test cases.
This paper details our experiences in establishing a robust power aware verification flow to catch low power Bugs early in the design cycle reducing the overall sign-off time. We present how the power aware formal verification, combined with a custom automatic property's extraction, helped us to obtain a simulation scenario independent analysis of power aware design functionality. The flow allows fast and specific LP checks without requiring any verification scenario setup. We share the results of our analysis, which highlight the bugs found using this methodology. We shall show how you can adopt this flow to make your power aware signoff comprehensive.
This paper details our experiences in establishing a robust power aware verification flow to catch low power Bugs early in the design cycle reducing the overall sign-off time. We present how the power aware formal verification, combined with a custom automatic property's extraction, helped us to obtain a simulation scenario independent analysis of power aware design functionality. The flow allows fast and specific LP checks without requiring any verification scenario setup. We share the results of our analysis, which highlight the bugs found using this methodology. We shall show how you can adopt this flow to make your power aware signoff comprehensive.
Event Type
Engineering Track Poster
TimeTuesday, June 255:21pm - 5:22pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP