Session

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Engineering Track Poster: Tuesday Engineering Track Poster Reception

Event TypeEngineering Track Poster

TimeTuesday, June 255:00pm - 6:00pm PDT

LocationLevel 2 Exhibit Hall

Topics

Presentations

5:00pm - 5:00pm PDT	Dashboard Model for Foundry Early Node Assessments using Synopsys Design.da Authors Luna Kang Jayson Seo Ann-Woo Lee James Ban
5:00pm - 5:01pm PDT	Powerdash: A Comprehensive Framework for SOC Power Analysis and Tracking Authors Vivek Joshi Atman Kar
5:01pm - 5:02pm PDT	Early Validation of Random TB using Formal Technology Author Euibong Jung
5:02pm - 5:03pm PDT	LINKED LIST PROOF ACCELERATOR Author Arjun Kumar
5:03pm - 5:03pm PDT	Empowering CDC analysis methodology with root cause analysis Authors Abdul Moyeen Manish Bhati
5:03pm - 5:04pm PDT	Ask-EDA: A conversational agent for tools, methodology, technology and design problems Authors Michael Kazda Bradley Sears Nicholas Shropshire Luyao Shi
5:04pm - 5:05pm PDT	AI-Enhanced Automated Optimization Workflow for HBM Interconnect on Interposer Authors Shineng Ma Hao Hu Bin Yu Keqing Ouyang Rodger Luo
5:05pm - 5:06pm PDT	A PVT-robust Design with Electronic/Photonic Co-simulation Engine for Microring-based DWDM 3-D Silicon Photonics Authors Chaerin Hong Luca Ramini Marco Fiorentino Ahsan Alam Zeqin Lu Raymond Beausoleil
5:06pm - 5:07pm PDT	Architecture Area Evaluation Tool Authors Ashishkumar Pal Adarsh TR Kavithaa Rajagopalan
5:07pm - 5:07pm PDT	Accelerating IO Liberty Generation through ML based Solution Authors Pawan Verma Anil-kumar Dwivedi Saurabh Srivastava Ajay Kumar Wei-Lii Tan
5:07pm - 5:08pm PDT	Safeguarding datapath security requirements through formal verification Authors Nicolae Tusinschi Keerthi Devarajegowda
5:08pm - 5:09pm PDT	Solving the antenna debug challenge in physical design verification Authors Rahul Sai T Govindaswamy Nermeen Hossam Anish Padhi Karishma Qureshi Gurpreet Lamba Rakesh reddy Katukuri
5:09pm - 5:10pm PDT	Resolving the seed promotion due to device layers derivation Authors Prachi Mrudula Atul Bhargava GAZAL SINGLA
5:10pm - 5:11pm PDT	Critical corners selection for standard cells LVF characterization using AI Authors Aravind Radhakrishnan Nair Ajay Kumar
5:11pm - 5:11pm PDT	SSN and EMA Bus Path Automation Authors Greg Ford Trinath Harikrishna
5:11pm - 5:12pm PDT	GPU Accelerated Harmonic Balance SPICE Simulation Authors Qikun Xue Chen Zhao
5:12pm - 5:13pm PDT	A Solution for Optimizing Customerized-MMB Authors Feilong Pan Minqiang Peng Keqing Ouyang Guohua Zhou Fengfeng Tang
5:13pm - 5:14pm PDT	Design Methodologies for Minimizing Local Routing Congestions in Low-level Metal Layers Authors Daeyeon Kim HONGSEOK CHOI Minkook Kim Sangyun Kim
5:14pm - 5:15pm PDT	A New Approach to Efficient Prelim Package Generation for Faster SOC Implementation Authors Bhupendra Singh Shoikat Das Saurabh Srivastava Anil Dwivedi
5:15pm - 5:15pm PDT	Future Proofing Chiplet Testbenches: Resilience in Multiprotocol Era Authors Kilaru Vamsikrishna Anunay Bajaj Shaikh Salehabibi Kilaru Vamsikrishna
5:15pm - 5:16pm PDT	Formal Tool Kit – A quick setup solution for formal analysis Authors Phanindra Ramanujapuram Rathnakar Madhukar Yerraguntla
5:16pm - 5:17pm PDT	A Novel Flow to Verify SoC Integration with Formal Property Verification Authors David Vincenzoni Marcello Dusini
5:17pm - 5:18pm PDT	DVD-aware STA and its silicon correlation results on 10nm test chip Authors Jongyoon Jung Hyun-seung Seo Byunghyun Lee Rajat Kukreja Ajay Sahoo Ji-Hun Kim Dae-Hun Jung Aniket Deshmukh
5:18pm - 5:18pm PDT	A Heuristic-Based Routing Methodology for Block-Level Memory Layout Routability Enhancement Authors Sichan Kim Seunghwan Lee
5:18pm - 5:19pm PDT	An Efficient Early Thermal Management Solution in 3DIC design Authors Ping Ding Guohua Zhou Keqing Ouyang Li Zou Shuqiang Zhang
5:19pm - 5:20pm PDT	An effective Hierarchical Top Scope Signal EM Flow for closing Large SOC Designs Authors Adish Mehta Rakesh Reddy Umberto Garofano Ratnakar Bhatnagar Steve Harvey
5:20pm - 5:21pm PDT	Towards a memory-address translation representation scheme Author Rathnakar Madhukar Yerraguntla
5:21pm - 5:22pm PDT	Early detection of low power related issues using formal verification Authors Andrea Lopinto Paola Baldrighi
5:22pm - 5:22pm PDT	MODEL BASED SYSTEM SEMICONDUCTOR ENGINEERING Authors Smriti Joshi Rosa Gragossian
5:22pm - 5:23pm PDT	Timing Takedown Reports 3 Author Lukas Pettersson
5:23pm - 5:24pm PDT	Physical Design With Intelligence Authors Bindu Rao Jagadeesh Gnanasekaran Prasenjit Ray Sai Prashant Anand Kumaraswamy Srinivas Jammula Raj Dua
5:24pm - 5:25pm PDT	Simulation and Measurement of MOMCAP Breakdown Risk Based on TCAD Authors Kun Zhou Jian Wang Tingting Hun Guohua Zhou Keqing Ouyang
5:25pm - 5:26pm PDT	Navigating Instruction Length Decode: TAP into IP using three pronged FV Trident Authors Vedprakash Mishra Aarti Gupta
5:26pm - 5:26pm PDT	Challenges Faced in Formal Based MSI: Tackle Formal Problem with a Formal Solution Authors Abhinav Parashar Ayush Jodh Parthasarathy Ramesh Harish Maruthiyodan Abhinav Parashar Gaurav Varshney
5:26pm - 5:27pm PDT	Autonomous Power Sequence validation solution for I/O using Solido Design Environment Authors ravinder kumar Fouad Mkalech Eric Mammi Vani Priya ravinder kumar (STMicroelectronics Pvt Ltd); Fouad Mkalech (Siemens); Eric Mammi (Siemens); Vani Priya (Siemens)
5:27pm - 5:28pm PDT	DIGITAL CONTINUITY FROM SEMICONDUCTOR EBOM TO MBOM AND BILL OF PROCESS Authors Smriti Joshi Manuel Rei
5:28pm - 5:29pm PDT	Advancements in Source Synchronous Design Implementation: An EDA Perspective Authors Keshavkumar Durgakeri Subba Ramkumar Reddy Annapalli Ponnada Naidu
5:29pm - 5:30pm PDT	Novel Preprocessing Technique for Data Embedding in Engineering Code Generation Using Large Language Models Authors Yu-Chen Lin Akhilesh Kumar Norman Chang Wen-liang Zhang Muhammad Zakir Jyh-Shing Jang
5:30pm - 5:30pm PDT	RDL and Bump Automation for Early EMIR Analysis In 2.5D, 3D and Single DIE Designs using RedHawk-SC Design ECO's Authors Arpan Bhowmik Raja Rama Chandra Rao Rishikanth Mekala Goda Ananth Somayaji
5:30pm - 5:31pm PDT	Scalable modeling of dynamic voltage compression on timing Author Tim Helvey
5:31pm - 5:32pm PDT	Matched Placement and Routing using Synchronized Unit Cell Array Authors Priyanka Madaan Akshita Bansal Ashwani sanwal Avinash Tripathi
5:32pm - 5:33pm PDT	A module based automation for AXI performance monitoring, performance extraction and protocol checking. Authors Naveen Srivastava Amresh Lenka Sekhar Dangudubiyyam
5:33pm - 5:33pm PDT	Machine Learning-based feasibility estimation of digital blocks for improved productivity in Analog-on-Top Back-End design flows Authors Gabriele Faraone Eugenio Serianni Dario Licastro Nicola DiCarolo Michelangelo Grosso Giovanna Franchino
5:33pm - 5:34pm PDT	Flash-based storage systems exploiting the data period for performance and security enhancement Authors Jung-Hoon Kim Suhwan Kim Daeun Oh
5:34pm - 5:35pm PDT	Challenges and Improvements in StandardCell OpenAccess Content for Analog Design Authors Anuradha Ray Frederic Avellaneda Stephan Weber Anuradha Ray
5:35pm - 5:36pm PDT	An Automated Solution for Streamlining Qualifications of Connectivity and DRC Across Diverse 3DIC Packaging Technologies Authors Taehyung Lee Woonggyu Lee Minkyung Kim Jihoon Park Hyojin Kim Changyoon Shin Jiseon Lee Yoojeong Yang Seungjae Jung Jongkoo kang Ahmed Saleh
5:36pm - 5:37pm PDT	WatsonX and DDB for AI Based Design Analytics and Visualization Authors Kerim Kalafala Nathaniel Hieter Douglas Keller
5:37pm - 5:37pm PDT	Implementing World's First Fully Integrated SoC Solution For Direct-To-Satellite IoT Connectivity Authors Sushanta Sarmah Alpesh Kothari Raghu Ram Gude
5:37pm - 5:38pm PDT	Auto Grouping And Improvement Of IR Critical Regions Using Unsupervised Learning Authors Arpan Bhowmik Abhishek Mahesh Chinchani Rishikanth Mekala Goda Ananth Somayaji
5:38pm - 5:39pm PDT	Accelerated Design Rule Learning for Silicon Photonics Authors Apoorva Vakil Romain Feuillette Timothy Miller
5:39pm - 5:40pm PDT	An efficient QA methodology for SRAM libraries Authors Hiroaki Koizumi Shuji Katayama Siddharth Ravikumar Mary Rayburn
5:40pm - 5:41pm PDT	A Data-Driven Automation Method of Liberty Model Characterization for Custom Cells Authors Dongsub Yoon Youngjin Ju Hyojin Choi
5:41pm - 5:41pm PDT	Enhancing and accelerating Verification with ad-hoc Python scripting Authors Edoardo Bollea Davide Sanalitro
5:41pm - 5:42pm PDT	Plug-n-Play Testbench environment for ARM Coresight SoC-400 Authors Sowmya V M Dhaval Panchal Lalithraj Mailappa Subramanian R Naveen Srivastava Sekhar Dangudubiyyam
5:42pm - 5:43pm PDT	Elevating BFM Capabilities: Authors Krunal Patel Shubham Agarwal Krunal Patel
5:43pm - 5:44pm PDT	Open Source AUTOSAR Classic Platform Author Moisés Urbina Fuentes
5:44pm - 5:45pm PDT	Peak Power Optimization using Active Datapath Operator Profiling Authors Vijay Tayal Sanchita Gupta Amit Dey Anil Mishra Hicham Anbar Mohammad Saif Ansari Manish Kumar
5:45pm - 5:45pm PDT	Risk Management in Volume Diagnostics Authors Pitchumani Guruswamy Vishnu Raj
5:45pm - 5:46pm PDT	Virtual Instrumentation Based Predictive Checks for Shift-Left Low Power Verification Authors Sachin Bansal Yi Liu Vijay Poosa M.Vaishnavi Reddy Nupur Gupta Vishal Keswani Amit Goldie Manish Goel
5:46pm - 5:47pm PDT	Integrated Calculation of Capacitances for Image Sensor Arrays and other Periodic Designs Authors Valery Axelrad Ognjen Milic
5:47pm - 5:48pm PDT	High Coverage QA for Process Variability Compensation in LVS Rule Deck Authors Heejae Lim Jaeyoung So Minho Jung Jimin Yeo Yunseong LEE Bonhyuck Koo Yongseok Lee Ahmed Saleh Mohamed Alimam
5:48pm - 5:48pm PDT	Avoiding CDC bugs introduced during Synthesis Optimizations and Netlist Transformations Authors suresh barla PARAS MAL JAIN harish Aepala anshul bansal Gunjan Mamania Kenneth Trejos
5:48pm - 5:49pm PDT	Analysis of Rare Failure Events: An Improved Scaled-Sigma Sampling Method Author Ning Lu
5:49pm - 5:50pm PDT	Machine Learning Optimization Switch cells. Author Sungsu Byun
5:50pm - 5:51pm PDT	An uptick on Automotive Safety Solutions using Cadence Implementation Tools Authors Jitendra Jain Ashwin Ramamurthy
5:51pm - 5:52pm PDT	Heterogeneous 3DIC Multi Voltage Timing Signoff Authors Tusharkant Mishra Ranjith V R Damodaran Trikkadeeri Santosh Varanasi
5:52pm - 5:52pm PDT	New SoC Creation Flow based on Extraction and recreating from previous SoC Authors Maël Rabé Chouki Aktouf
5:52pm - 5:53pm PDT	Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory Authors Jeongyoon Lee Kyeongrok Jo Seunghwan Lee Seungkwang Hong Heejin Bae Jiwon Woo Youngwook Kim Jungyun Choi
5:53pm - 5:54pm PDT	Next-Gen comprehensive IR analysis with Ansys SigmaAV Authors Pranav Ranganathan Medha Kulkarni Chip Stratakos Veshal Sridhar Mallik Vusirikala
5:54pm - 5:55pm PDT	Tapeout Data Preservation and automatic archival tagging for Optimal Disk Space Management Author Yamini Ravishankar
5:55pm - 5:56pm PDT	A Novel Automation flow to generate SV-UVM Testbench with integrated BFMs Presenters Parthasarathy Ramesh Sagar Jogur Raminder Kaur Atul Lele
5:56pm - 5:56pm PDT	Coverage-based FV signoff – The complete cleanup methodology Authors Gilboa Alin Daher Kaiss Anmol Patel Aarti Gupta Gavriel Gavrielov
5:56pm - 5:57pm PDT	Development of SystemC-based Security VP for In-House SED SSD Firmware Verification and Application of libFuzzer Presenter CHANGWON KIM
5:57pm - 5:58pm PDT	True-Hybrid SaaS Cloud Architectures for EDA Workloads Authors Ravi Poddar Amit Varde Nupur Bhonge
5:58pm - 5:59pm PDT	Automated Constraint Promotion Methodology from IP to SoC for Complex Designs Authors Mallik Devulapalli Rimpy Chugh
5:59pm - 6:00pm PDT	Advanced Static Methodology for Complete Connectivity and Glitch Signoff Authors Abhishek Ghate Saurav Choudhary Vikas Sachdeva

DAC 2024