Presentation
Virtual Instrumentation Based Predictive Checks for Shift-Left Low Power Verification
DescriptionSynopsys VC LP is a static low power verification checker which helps to verify consistency between UPF and design throughout the design flow.
Traditional use models of VC LP allow to make sure UPF is correct and complete at RTL stage and at netlist stage, the low power cells (multi-voltage or MV cells) such as Isolation and Level Shifter inserted are structurally and electrically correct.
New electrical issues introduced after MV cell insertion are caught only at netlist. There is an increasing demand to catch netlist level low power issues at the RTL stage itself and to reduce noise by predicting post-synthesis behavior.
Virtual instrumentation-based flow in VC LP shifts left the low power verification by virtually instrumenting the MV cells in the design based on the power intent leading to more accurate verification of the design at RTL stage.
VC LP has achieved ~99% accuracy in predictive checkers w.r.t netlist runs at customer design.
One customer has enabled this feature on 100+ sub-systems and SOC which matched netlist behavior at RTL stage especially for back-to-back ISO/LS cases. This flow is also gaining traction at various elite customers.
Traditional use models of VC LP allow to make sure UPF is correct and complete at RTL stage and at netlist stage, the low power cells (multi-voltage or MV cells) such as Isolation and Level Shifter inserted are structurally and electrically correct.
New electrical issues introduced after MV cell insertion are caught only at netlist. There is an increasing demand to catch netlist level low power issues at the RTL stage itself and to reduce noise by predicting post-synthesis behavior.
Virtual instrumentation-based flow in VC LP shifts left the low power verification by virtually instrumenting the MV cells in the design based on the power intent leading to more accurate verification of the design at RTL stage.
VC LP has achieved ~99% accuracy in predictive checkers w.r.t netlist runs at customer design.
One customer has enabled this feature on 100+ sub-systems and SOC which matched netlist behavior at RTL stage especially for back-to-back ISO/LS cases. This flow is also gaining traction at various elite customers.
Event Type
Engineering Track Poster
TimeTuesday, June 255:45pm - 5:46pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP