Presentation
Calibre Autowaiver for Early DRC & DFM Analysis In Big Die Designs
DescriptionWith the exponential growth in design complexity, stringent timelines in Chip design cycle closure, the process advancements and increased runtimes in both physical design sign-off verification and Quality Analysis are constantly driving the need for faster and more efficient physical verification (PV) strategies.
Early PV analysis ensures designers to be able to quickly and easily analyze the critical issues. They can find and fix the root cause of errors in an efficient, accurate and fast manner. Fixing critical DRC and DFM issues later in the project cycle becomes more challenging. Our paper describes some of the efficient techniques which enable the faster Chip design sign-off convergence.
Early PV analysis ensures designers to be able to quickly and easily analyze the critical issues. They can find and fix the root cause of errors in an efficient, accurate and fast manner. Fixing critical DRC and DFM issues later in the project cycle becomes more challenging. Our paper describes some of the efficient techniques which enable the faster Chip design sign-off convergence.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP