Presentation
An Effective Method of Evaluating Chip Power Noise in System-level with iCPM
DescriptionWith the continuous advancement of advanced chip packaging technology, the excellent performance of package core power plays a pivotal role in the operation of the entire chip. Especially for high-performance 2.5D and 3D large-scale ICs, the efficient simulation of core power poses significant challenges.
Many indicators of IP power noise are targeted at M0 within the die. Backend engineers can utilize a package subckt model to simulate dynamic and static IR drops to verify if the power noise at M0 meets the requirements of the indicators. But package engineers typically only simulate power noise at the bumps limited by tools and methods.
This paper introduces a fast method for evaluating chip power noise using iCPM. The iCPM is generated by RedHawk-SC with several probe points on M0. Subsequently, package engineers can construct a circuit using iCPM + package model + PCB model. Simulating power noise at M0 via spice simulation only takes a few minutes. This method significantly improves simulation efficiency.
Many indicators of IP power noise are targeted at M0 within the die. Backend engineers can utilize a package subckt model to simulate dynamic and static IR drops to verify if the power noise at M0 meets the requirements of the indicators. But package engineers typically only simulate power noise at the bumps limited by tools and methods.
This paper introduces a fast method for evaluating chip power noise using iCPM. The iCPM is generated by RedHawk-SC with several probe points on M0. Subsequently, package engineers can construct a circuit using iCPM + package model + PCB model. Simulating power noise at M0 via spice simulation only takes a few minutes. This method significantly improves simulation efficiency.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP