Presentation
Advancements in Source Synchronous Design Implementation: An EDA Perspective
DescriptionAs we move towards lower-technology nodes, the challenges in design implementation intensify & enhancing design methodologies and algorithms becomes crucial. By encouraging the integration of different stages, we can significantly improve the implementation process. We present an innovative methodology for implementing a source-synchronous design by integrating an extra stage into our conventional APR flow, strategically situated between the floorplan and placement stages during the design implementation. Our presented solution utilizes a source-synchronous design topology, [SSD Flow], comprising two distinct stages. Initially, we traverse the critical signal nets, followed by the execution of tailored clock routing that adheres to specified rules and constraints. This articulated approach systematically navigates timing intricacies while proactively mitigating crosstalk and noise issues, ultimately optimizing the design. The main objective is to devise a methodology to simplify the implementation process and achieve an enhanced Quality of Results (QoR). Our proposed methodology has significantly streamlined the design implementation process, yielding substantial improvements. Remarkably, our approach has showcased a substantial improvement in Turnaround Time (TAT), featuring a commendable reduction of 2 weeks. From the implementation perspective, our methodology has delivered noteworthy and promising outcomes, including a 48% decrease in latency, a 59.20% reduction in data path delay, a 39.6% enhancement in dynamic power, a 50% reduction in data path depth, and a 55.5% decrease in clock path depth.
Event Type
Engineering Track Poster
TimeTuesday, June 255:28pm - 5:29pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP