Presentation
AI-Driven Frontiers in Energy-Efficient Neural Processor Design
DescriptionWe examine an advanced IMC NPU design through a detailed case study, illustrating the application of a novel design space exploration methodology. This method integrates adaptive body bias for PVT pruning with a Cerberus-guided routing and floor planning design space exploration. The synergy of these techniques culminates in a substantial enhancement of compute density and energy efficiency in the IMC NPU. Our findings reveal a tenfold improvement in vital performance metrics when compared to conventional digital NPUs. This work not only underscores the viability of IMC NPU designs in high-efficiency applications but also exemplifies the use of AI/ML in refining hardware design processes to achieve unprecedented performance gains.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP