Presentation
Overcoming the Growing Challenge of IR Drop by Effective Power Grid Enhancement during Chip Finishing
DescriptionIntegrated circuit (IC) Power management is a growing challenge for both designers and manufacturers at advanced process nodes. We introduce an analysis-based solution during chipfinishing flow. This innovative solution provides automated DRC-clean layout modifications that reduce IR drop without negatively impacting performance and area.
Key metrics for a PnR flow focus on design performance, power, and area (PPA) goals. Using the solution, designers first analyze a chip for EMIR hotspots, then apply automated layout modifications to reduce resistance in these specific areas. These Correct-by-Construction modifications are based on a thorough understanding of available routing tracks and signoff DRC rules, significantly reducing costly design iterations between PnR tools and the final physical verification solution.
In this presentation, We demonstrate integration of the collaborative development of a Calibre DesignEnhancer tool into our design flow with Siemens to showcase the before and after EMIR results for an advanced node that shows 30% reduction in IR drop. This reduces the iterations required to correct the IR drop violations and eliminating iterations between PnR and physical verification, the DRC-clean results provided by the Calibre DesignEnhancer tool that significantly reduce the time pressure of final design closure while enhancing design quality of results for EMIR improvement.
Key metrics for a PnR flow focus on design performance, power, and area (PPA) goals. Using the solution, designers first analyze a chip for EMIR hotspots, then apply automated layout modifications to reduce resistance in these specific areas. These Correct-by-Construction modifications are based on a thorough understanding of available routing tracks and signoff DRC rules, significantly reducing costly design iterations between PnR tools and the final physical verification solution.
In this presentation, We demonstrate integration of the collaborative development of a Calibre DesignEnhancer tool into our design flow with Siemens to showcase the before and after EMIR results for an advanced node that shows 30% reduction in IR drop. This reduces the iterations required to correct the IR drop violations and eliminating iterations between PnR and physical verification, the DRC-clean results provided by the Calibre DesignEnhancer tool that significantly reduce the time pressure of final design closure while enhancing design quality of results for EMIR improvement.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP