Presentation
Faster Timing Closure of Multiple Power Domains Based Designs with SMVA
DescriptionMulti-voltage SoC's with uncorrelated supplies are becoming predominantly common with a lot of devices coming up in the market with low power requirements. Here, Non-timing critical blocks are designed at lower voltage (power saving) and High-performance blocks are designed at higher voltage (desired performance). In such Low power SOC's, Timing Closure poses a bigger challenge with tight schedules and predictable results before tape-out as timing signoff of the chip has to be done on multiple corners and multiple modes (MCMM). Single voltage timing analysis is easier. But, with the multi-level supply voltage and dynamic scaling features, the timing analysis complexity increases because timing signoff has to be done additionally on cross-voltage paths, which are not guaranteed to be worst case timing at either voltage corner. Multi-voltage designs need exhaustive analysis of cross voltage domain paths to make sure all worst-case paths are identified under all voltage combinations. With numerous operating PVT corners, timing analysis across corners becomes further challenging. Synopsys Primetime's based Simultaneous multi-voltage aware analysis (SMVA) was helpful to attain this, to do the analysis of all cross-domain paths under all voltage scenarios in a single run, without the need for margining that can add pessimism. This paper describes Primetime based SMVA methodology for predictable and faster Timing Closure of Multiple Power Domains Based Designs.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP