Presentation
An Integrated Behavioral Modeling Method for Mixed Signal IPs
DescriptionThe shrinking technologies have paved the path for complex devices having various functionalities integrating various IPs in a single SoC and hence, complex clocking structure and efficient power management in AMS IP are gaining popularity. The same design complexity is reflected in HDL behavior model like timing from internal clock, real modeling, power aware modeling etc. There is need of robust behavior modeling of these complex IPs, to enable accurate and efficient functional check along with timing.
In this paper, the challenges and shortcomings associated with modeling of complex AMS IPs for timing simulations are discussed, along with the proposed methodology. It has also been demonstrated how this methodology handles the correct data latching issue in case of negative timing checks present in the design, without compromising on any advanced feature supported in the model.
In this paper, the challenges and shortcomings associated with modeling of complex AMS IPs for timing simulations are discussed, along with the proposed methodology. It has also been demonstrated how this methodology handles the correct data latching issue in case of negative timing checks present in the design, without compromising on any advanced feature supported in the model.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP