Presentation
Efficient HBM Channel Design in 2.5D Silicon Interposer with Signal Integrity Optimization
DescriptionHigh Bandwidth Memory (HBM) in 2.5D interposers is to address the need for increased memory bandwidth in AI and HPC applications. HBM channel design is crucial for achieving the high-speed data transfers. However, routing such a channel is challenging due to the tight interconnections and the need to manage signal integrity (SI) in a compact space. It is common to take months to route a HBM channel and run multiple iterations to meet the SI requirement. The paper proposes an efficient flow including steps to quickly explore routing pattern during the pre-layout stage with Xpeedic Metis tool, auto route the HBM channel with Synopsys 3DIC Compiler, and run post-layout SI analysis with integrated Xpeedic Metis. The demo example shows tremendous time saving with the new flow.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP