Presentation
Pnr implementation challenges in 3d ic
DescriptionTSVs creates repeated placement and route blockages in design.
Special care needed to deal with floorplan and power plan challenges to handle TSV.
With increase number of blockages and TSV islands, pre-place cell addition and power plan run time increases.
Module splits near TSV, makes difficult for timing and m-bit merging.
Route Detoured on TSV area causes timing degradation.
Bigger IP need special planning, to ensure adequate power supply in TOP die.
With increased PnR runtime , handling pnr in 3D is difficult part.
Special care needed to deal with floorplan and power plan challenges to handle TSV.
With increase number of blockages and TSV islands, pre-place cell addition and power plan run time increases.
Module splits near TSV, makes difficult for timing and m-bit merging.
Route Detoured on TSV area causes timing degradation.
Bigger IP need special planning, to ensure adequate power supply in TOP die.
With increased PnR runtime , handling pnr in 3D is difficult part.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP