Presentation
Formal CDC Glitch Check - Advanced Sign Off Solution
DescriptionModern System-on-Chips (SoCs) are complex structures that integrate multiple clocks and Clock Domain Crossing (CDC) paths.
Glitch propagation is a critical aspect of CDC, as glitches can cause metastability, leading to unpredictable behavior and data corruption.
A combination of process technology trends coupled with increased intervention by synthesis tools in logic generation can lead to cases in which a design that is CDC-clean at RTL stage fails in the post-synthesis gate-level netlist.
This paper presents such a case along with the tools that were used to analyze potential CDC violations.
We will describe a formal glitch qualification engine that was used for the final verdict.
Additionally we will examine the root cause that led to this scenario and provide recommendations to prevent similar occurrences in the future.
Glitch propagation is a critical aspect of CDC, as glitches can cause metastability, leading to unpredictable behavior and data corruption.
A combination of process technology trends coupled with increased intervention by synthesis tools in logic generation can lead to cases in which a design that is CDC-clean at RTL stage fails in the post-synthesis gate-level netlist.
This paper presents such a case along with the tools that were used to analyze potential CDC violations.
We will describe a formal glitch qualification engine that was used for the final verdict.
Additionally we will examine the root cause that led to this scenario and provide recommendations to prevent similar occurrences in the future.
Event Type
Front-End Design
TimeMonday, June 242:00pm - 2:15pm PDT
Location2010, 2nd Floor
Design
Engineering Tracks
Front-End Design