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Organization

Marvell
Contributors
Bertram Bradley
Justin Conklin
Noam Eshel Goldman
Patricia Fong
Greg Ford
Umberto Garofano
Sushant Hajare
Trinath Harikrishna
Tim Helvey
Richard Kessler
Adish Mehta
Liad Nehama
Lavanya Padmanabhuni
Lukas Pettersson
Santhosh Ramappa
Yamini Ravishankar
Rakesh Reddy
Shourya Shukla
Sainarayanan Suryanarayanan
Dean Wallace
Presentations
DAC Pavilion Panel
Advancing Chip Security to Meet Heightened Requirements
Security
Back-End Design
An effective Hierarchical STA solution for closing Large SoC Design
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
An effective Hierarchical Top Scope Signal EM Flow for closing Large SOC Designs
Back-End Design
Embedded Systems
Front-End Design
IP
DAC Pavilion Panel
Blackout – Managing kW Power Budgets
Design
Front-End Design
Formal CDC Glitch Check - Advanced Sign Off Solution
Design
Engineering Tracks
Front-End Design
Back-End Design
History, Present, and Future of STA: A Travel Through Timing
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Memory Clusters – Divide the design and optimize MBIST insertion efforts
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Predicting Computer Resource Needs using Machine Learning and Conventional Design
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Scalable modeling of dynamic voltage compression on timing
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
SSN and EMA Bus Path Automation
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Tapeout Data Preservation and automatic archival tagging for Optimal Disk Space Management
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Timing Closure Methods on 5nm Design Challenges
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Timing Robustness: A Way forward for analyzing timing-voltage sensitive paths for accounting IR-Drop Variations
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Timing Takedown Reports 3
Back-End Design
Embedded Systems
Front-End Design
IP