Presentation

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Shift Left Detection and Root Cause Analysis of Synthesis Optimized Registers at RTL Level

DescriptionThe presentation focuses on bridging the gap between RTL designers and Implementation engineers. Removal of registers during the synthesis stage without providing any root cause analysis poses significant challenges for Implementation engineers late in the cycle. At the same time, currently there is no alternative for RTL designers to get early insights into register optimizations. Presentation highlights the challenges in verifying register optimization and proposes a shift-left methodology using Hyper-convergence to accurately detect and root cause synthesis optimized registers at early in the RTL stage itself. It also outlines future work to extend these methodologies to solve other implementation tool problems.

Presenters

Sathappan Palaniappan