Presentation
Design Constraint Strategy For Dealing With Cascaded Clock MUX Structures
DescriptionThe presence of multiple and cascaded clock MUX structures can be seen in complex RTL/digital desings. The existing CDC static verification tools, Synthesis tools and Static Timing Analysis (STA) tools have a hard time analyzing the operation modes of clock multiplexers (clock MUX in short), especially if they are glitch free switching circuits that may not resemble a simple multiplexer to the tools. For uch clock MUX structures, relevant design constraints (or SDCs) need to be added to guide the static tools. In this proposal we have a series of well-defined generated clock and logically exclusive constraints that will help cover all the combinations of clock propagations through any complex clock MUX structure in the design. This will enable smooth CDC, synthesis and timing verification of the design considering all the clocks input to the clock MUX, in an accurate manner. This technique yields accurate results from an STA and a synthesis perspective. This technique helps to reduce the number of case analysis modes needed (which is essentially to propagate only one fixed clock through a clock MUX in that mode), meaning that it can do the heavy lifting of all the analysis modes at one go, thereby reducing the turnaround time considerably. The coverage of all combinations of clocks is now possible in one single CDC static verification run, which also eliminates the noise in CDC reports where there were overlapping violations across analysis modes previously. With such promising results, there is also scope for automation of this technique provided the relevant data is available as input.
Event Type
Front-End Design
TimeWednesday, June 2611:42am - 12:00pm PDT
Location2010, 2nd Floor
AI
Design
Engineering Tracks
Front-End Design