Presentation
Leveraging Formal Verification to Create, Reproduce, Verify Design Scenarios from Simulation Wave-dump
DescriptionAs designs become increasingly complex, ensuring that corner cases are properly verified is a critical challenge. While traditional verification techniques like Constrained Random Verification (CRV) and formal methodology have been used for this process, they both have their limitations. Functional simulation is time and resource-intensive, and it is not exhaustive. The formal verification approach, though exhaustive, requires prior knowledge for creating the System Verilog properties to verify. To address this challenge, we need to explore innovative verification techniques that can help effectively verify complex designs and ensure that they meet the desired specifications. Waveforms and timing diagrams are commonly used by designers to represent design behavior over multiple cycles. To help capture information from failing scenario Wave-dumps or user-defined timing scenarios, we've developed a utility that quickly converts timing data into a System Verilog Property. This enables designers to independently reproduce and verify scenarios in a formal verification environment with ease. The proposed approach reduces scenario regeneration time by up to 180 times concerning Functional Simulation Verification.
Event Type
Front-End Design
TimeMonday, June 241:45pm - 2:00pm PDT
Location2010, 2nd Floor
Design
Engineering Tracks
Front-End Design