Presentation
Shift Left with Improved Power-Awareness in RTL Stage Design for Early Design Verification
SessionAdvanced Verification
DescriptionRegister Transfer Logic (RTL) of Digital on Top (DoT) SoC designs limited to logical integration.
Conventionally the early simulation framework involving digital RTL does not have native power comprehension. The Power Intent (PI) is captured through CPF/UPF integration.
The Power and Ground (PG) IO cells are physical only cells (no logical connectivity), they are not inferred or instantiated in RTL.
This results in lack of
BIASFET connectivity at RTL stage of design à BIASFET is the ESD trigger generated in a PGIO that drives the primary protection devices in IO cells.
Low Power (LP) checks through PGIO paths.
It causes conventional DMS/AMS simulation setup to fail if it involves IO functionality.
In most mixed-signal embedded processing SoCs, even the power-up fails à BIASFET connectivity impacts external reset propagation.
The proposed solution is Compatible with standard/semi-custom implementation flows.
Complete coherence across design, implementation and verification flows.
Enables concurrent execution of LP verification and Physical Design (PD) cycles.
Enables early generation of Power Aware (PA) netlist, hence early verification of power intent with PG I/Os aware RTL.
Eliminates manual work-arounds in traditional LP mixed-signal/analog verification.
Verifying the chip level ESD integration across digital domains at early stage of the design using PA-RTL and avoid risk due to late finding of ESD triggering risk in the designs.
Debugging of ESD protection circuit integration issues at early stage.
As a result, overall design cycle time and RTL freeze quality improved.
Conventionally issues with ESD architecture including BIAS connectivity and can only be identified at post synthesis Gate Level (GL) stage à At least 3 months later than RTL stage.
Conventionally the early simulation framework involving digital RTL does not have native power comprehension. The Power Intent (PI) is captured through CPF/UPF integration.
The Power and Ground (PG) IO cells are physical only cells (no logical connectivity), they are not inferred or instantiated in RTL.
This results in lack of
BIASFET connectivity at RTL stage of design à BIASFET is the ESD trigger generated in a PGIO that drives the primary protection devices in IO cells.
Low Power (LP) checks through PGIO paths.
It causes conventional DMS/AMS simulation setup to fail if it involves IO functionality.
In most mixed-signal embedded processing SoCs, even the power-up fails à BIASFET connectivity impacts external reset propagation.
The proposed solution is Compatible with standard/semi-custom implementation flows.
Complete coherence across design, implementation and verification flows.
Enables concurrent execution of LP verification and Physical Design (PD) cycles.
Enables early generation of Power Aware (PA) netlist, hence early verification of power intent with PG I/Os aware RTL.
Eliminates manual work-arounds in traditional LP mixed-signal/analog verification.
Verifying the chip level ESD integration across digital domains at early stage of the design using PA-RTL and avoid risk due to late finding of ESD triggering risk in the designs.
Debugging of ESD protection circuit integration issues at early stage.
As a result, overall design cycle time and RTL freeze quality improved.
Conventionally issues with ESD architecture including BIAS connectivity and can only be identified at post synthesis Gate Level (GL) stage à At least 3 months later than RTL stage.
Presenters
Event Type
Front-End Design
TimeTuesday, June 251:45pm - 2:00pm PDT
Location2010, 2nd Floor
Design
Engineering Tracks
Front-End Design