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Session

Front-End Design: Advanced Verification
Session Chair
Dave Rich
Siemens
DescriptionJoin us to learn about new strategies in the catch-up game verification engineers play daily with the increasing design complexity and tighter schedules. In this session, presenters will share their wisdom across HLS, FuSa and hardware/software verification.
Event TypeFront-End Design
TimeTuesday, June 251:30pm - 3:00pm PDT
Location2010, 2nd Floor
Topics
Design
Engineering Tracks
Front-End Design
Presentations
1:30pm - 1:45pm PDTUse UVM for AMS DFT through IEEE 1687 Procedural Description Language
Presenters
Hitu Sharma
Geert Seuren
Rahul Lodwal
1:45pm - 2:00pm PDTShift Left with Improved Power-Awareness in RTL Stage Design for Early Design Verification
Presenters
Penchalkumar Gajula
Lakshmanan Balasubramanian
Gaurav Varshney
Sooraj Sekhar
Siddharth Sarin
Ruchi Shankar
2:00pm - 2:15pm PDTEnhancing Quality and Reducing Verification Effort for RTL Implementations against High-Level C/C++ Models using Formal Equivalence
Presenters
David Vincenzoni
Gianluca Rigano
Gaetano Raia
Maurizio Martina
2:15pm - 2:30pm PDTA Distributed Co-Simulation Environment and its Application in HW-FW Verification
Presenters
Nitin Pundir
Pretty Jacob
Arun Joseph
Viresh Paruthi
Sandeep Korrapati
Ali El-Zein
Zoltan Hidvegi
Bodo Hoppe
2:30pm - 2:45pm PDTWho watches the watchman? FuSa Verification of DCLS configuration through Formal and Static checks
Presenters
Sayandeep Sanyal
Avinash Pandey
Srobona Mitra
Sathish Manickam
Arunava Dutta
Deepak Baranwal
2:45pm - 3:00pm PDTSystematic Flow on AC Scan Timing/ATPG Constraint Generation
Presenters
Chen Yuan Kao
Yi Hsuan Chiu