Presentation
Augmenting IP/SOC Verification Exhaustiveness with BER Transformer infused Deep Learning Model
DescriptionIn the realm of ever evolving Semiconductor technology landscape with complex SoC's and Systems , integration of Chat GPT like AI Transformers in IP/SoC Design Verification could potentially revolutionize a transformative wave of automating verification there by contributing to increased robustness of designs.
IP and SOCs underpin many modern electronic systems like HPC/AI and Automotive SoC's. While functional correctness is crucial, it no longer suffices for real-world applications and usage. In this paper we have explored to utilize the power of light-weight generative AI BER Transformer Model in verification as it redefines the possibilities of how we interact with textual data, including hardware design specifications and taking verification to completeness by suggesting extra scenarios for Performance and Security aspects . It bridges the gap between 'what' a system does, 'how well' it performs, and 'how securely' it operates and addresses the grey areas in system level verification which cannot be captured at IP or sub-system level.
We can scale this model to SOC level and try to address verification challenges for miscellaneous SOC IP's like GPIO,DFT mux, Lower Power Elements and Safety Elements.
This paper highlights the power of using Generative AI in verification, Augmenting AI with verification can help us catch bugs/issues early in the verification life cycle.
IP and SOCs underpin many modern electronic systems like HPC/AI and Automotive SoC's. While functional correctness is crucial, it no longer suffices for real-world applications and usage. In this paper we have explored to utilize the power of light-weight generative AI BER Transformer Model in verification as it redefines the possibilities of how we interact with textual data, including hardware design specifications and taking verification to completeness by suggesting extra scenarios for Performance and Security aspects . It bridges the gap between 'what' a system does, 'how well' it performs, and 'how securely' it operates and addresses the grey areas in system level verification which cannot be captured at IP or sub-system level.
We can scale this model to SOC level and try to address verification challenges for miscellaneous SOC IP's like GPIO,DFT mux, Lower Power Elements and Safety Elements.
This paper highlights the power of using Generative AI in verification, Augmenting AI with verification can help us catch bugs/issues early in the verification life cycle.
Event Type
Front-End Design
TimeWednesday, June 2611:06am - 11:24am PDT
Location2010, 2nd Floor
AI
Design
Engineering Tracks
Front-End Design