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Evaluating power, performance, and area for standard cell libraries from different IP providers
DescriptionStandard cell libraries are the foundation to implementing the largest, most advanced digital designs today. Selecting the correct standard cell library for a design is an important step that has lasting implications that will impact final power, performance, and area (PPA) metrics of the chip, as well as tapeout schedule.
Liberty (.lib) models encapsulate PPA characteristics of standard cell libraries, but profiling PPA of .libs from different sources is difficult because of varying cell types, pins, timing arcs, and structural differences between libraries. Synthesizing a test design with different .libs to measure PPA requires a schedule overhead, and results will be heavily influenced by the type of test design used.
This paper discusses a methodology for comparing PPA at the library level, where a library analysis tool is utilized to help correctly align different cell, pins, timing arcs, and other library information between libraries, so that apples-to-apples comparisons can be made between cell types of interest. We also cover the different visualization and analysis templates that are useful for benchmarking libraries.
This approach enables users to quickly and correctly profile different .libs, select the correct library for the use case, to improve chip-level PPA and design closure schedule.
Event Type
IP
TimeMonday, June 242:00pm - 2:15pm PDT
Location2012, 2nd Floor
Topics
Engineering Tracks
IP