Presentation
Low-Cost Built In Self Test IP for Nextgen Continuous Time Sigma Delta ADCs
DescriptionWe present a complete on-chip built-in self-test (BIST) technique for testing a high-performance Continuous Time Sigma Delta Analog to Digital Converters (CTSD ADCs). A pre-stored pulse density modulated digital bitstream is filtered and applied to an inherently linear mixed signal FIR filter for stimuli generation. The analog sigma delta modulator output is processed by a digital filter chain and a single bin Discrete Fourier Transform (DFT) computer to accurately determine the spectral content and related performance figures. The proposed fully on-chip architecture obviates the need of an accurate analog signal generator and post processing on chip. Its area overhead is less than 5% of the total ADC area. The BIST circuit is plug and play with its operation independent of the sigma delta modulator and ADC specification. As the presented design is mostly digital, it is highly technology independent, enabling very short development times.
Event Type
IP
TimeTuesday, June 2511:15am - 11:30am PDT
Location2010, 2nd Floor
Engineering Tracks
IP