Presentation
An All-Digital Transient Filter IP for Serial Links
DescriptionAn on-chip all-digital transient filter IP is proposed as a replacement of an off-chip, external to chip RC circuit for glitch filtering. This is mandatory for EMC compliance and to filter-out transient artifacts due to impedance mismatches. The proposed filter area is very low and can be accommodated in existing design of serial link PHY receivers. It has low insertion latency, does not vary the signal transition width and preserves the signal width/duty cycle of the received signal. The high figure of merit all-digital filter completely replaces the conventional RC low pass filter. The prior analog RC filter not only adds inertia to the system, but also occupies physical board space. Muti-channel systems will benefit a lot and become less cumbersome. The proposed design is all-digital and thus highly technology independent, enabling very short development times. It has been deployed successfully in the MIPI I3C controller and tested with glitchy transitions in both SCL & SDA signals.
Event Type
IP
TimeTuesday, June 2511:30am - 11:45am PDT
Location2010, 2nd Floor
Engineering Tracks
IP