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IP: Methodologies for Streamlining SoC Design Challenges
DescriptionSoC design poses several challenges in terms of design flow and methodologies. The use of advanced and automated methods is crucial, especially for compute-intensive workloads. This session presents various topics on design methodologies such as: accelerating placement-aware timing closure for NOCs, an open-source design flow promising support for generative AI, accelerating DRC checks, CDC multimode signoff methodology, droop mitigation and scalable sign-off/QA flow.
Event TypeIP
TimeTuesday, June 2510:30am - 12:00pm PDT
Location2010, 2nd Floor
Topics
Engineering Tracks
IP