Presentation
Interfacing High-Voltages Directly to Low Power CMOS Process Die for RF, MEMs and Analog Applications
DescriptionSensors and signal converters exist at the boundaries of digital and analog components, usually with voltage barriers in the boundaries. However, the foundry technology of sensors hasn't scaled as fast as logic process with its advancement into lower voltage and power. Many MEMs and RF applications still need voltage levels >10V for normal operation, requiring additional discrete components into a system board to down-shift the higher voltage (HV) RF and Analog domains to the low voltage CMOS products.
Certus Semiconductor's HV solution were designed in the standard CMOS process nodes, without requiring extra masks, technology, or layers. This capability has enabled PMIC, MEMs and RFIC developers to bring directly to die, any HV signal that would have otherwise required off-chip components to downgrade the voltage levels to <5V, thus providing customers a direct competitive edge in the marketplace of HV RF, analog and MEMs. These IO solutions have been proved with silicon verification with the embedded ESD protection.
During the design process, Certus utilizes Siemens' Calibre DRC for design guidance, ensuring the monitoring of specialized layouts. Additionally, Analog FastSPICE Platform, a foundry-certified tool across various process technologies from major foundries, for designing and verifying parasitic models during chip finalization.
Certus Semiconductor's HV solution were designed in the standard CMOS process nodes, without requiring extra masks, technology, or layers. This capability has enabled PMIC, MEMs and RFIC developers to bring directly to die, any HV signal that would have otherwise required off-chip components to downgrade the voltage levels to <5V, thus providing customers a direct competitive edge in the marketplace of HV RF, analog and MEMs. These IO solutions have been proved with silicon verification with the embedded ESD protection.
During the design process, Certus utilizes Siemens' Calibre DRC for design guidance, ensuring the monitoring of specialized layouts. Additionally, Analog FastSPICE Platform, a foundry-certified tool across various process technologies from major foundries, for designing and verifying parasitic models during chip finalization.
Event Type
IP
TimeTuesday, June 2511:45am - 12:00pm PDT
Location2010, 2nd Floor
Engineering Tracks
IP