Presentation
Beyond Digital: Innovation in symbolic simulator to empower IO analog circuit validation
DescriptionInterface IPs are an important part of any integrated circuit design that needs to communicate with the outside world or other integrated circuits. Out of many design views of IO libraries (e.g., GPIO, I2C, I3C, etc.) the logical views have special importance as it defines the basic function of the design. The functionality in these views should be verified to the best possible extent as broken functionality leads to one of the heaviest costs a design house may pay in terms of silicon failures. Symbolic simulation provides unique and powerful solutions to the plethora of technical challenges faced by logic verification engineers of interface IPs. The Synopsys ESP uses symbolic simulation technology to offers high-quality equivalence checking for full-custom designs.
In this paper, Synopsys ESP has been explored to validate complex interface IP's. ESP is quite known for equivalence checking of Standard cells & Memories, which is mostly having digital blocks. On another side - Interface IPs consists of bunch of analog blocks along with digital which makes it more complex for equivalence checking. Resolving analog-blocks is complex for ESP and sometimes resolved to incorrect logic, so we are showcasing the challenges faced with analog-blocks of Interface IP's along with their proven solutions and showcasing the advantages it brought within ESP broadening its Analog Design validation coverage.
In this paper, Synopsys ESP has been explored to validate complex interface IP's. ESP is quite known for equivalence checking of Standard cells & Memories, which is mostly having digital blocks. On another side - Interface IPs consists of bunch of analog blocks along with digital which makes it more complex for equivalence checking. Resolving analog-blocks is complex for ESP and sometimes resolved to incorrect logic, so we are showcasing the challenges faced with analog-blocks of Interface IP's along with their proven solutions and showcasing the advantages it brought within ESP broadening its Analog Design validation coverage.
Event Type
IP
TimeTuesday, June 252:30pm - 2:45pm PDT
Location2012, 2nd Floor
Engineering Tracks
IP