Presentation
Enabling Protocol Validation of High Speed Serial Links using SerDes to transfer data between PHY Chip and Link layer on FPGA
DescriptionEver increasing demand for higher data transfer speed leads to evolution of new Serial link protocols and advancement in existing one. Implementation and support of these Serial link protocols require evolution of PHY and Controller. PHY IPs require to be tested upfront on Silicon Chip (PHY IPs are Analog- Mixed Signal IPs) for every technology node/Foundry. Data from this PHY Chip needs to be transferred to FPGA for validation with Controller. Increase in bit rate poses a significant challenge due to need for large number of GPIOs in the PHY chip. This increased number of GPIOs increase the size in PAD limited PHY Chip which increases the cost. To address this problem, proposed solution is to use lanes of lower speed SerDes to transfer data between PHY Chip and FPGA instead of multiple parallel GPIOs
Event Type
IP
TimeTuesday, June 252:45pm - 3:00pm PDT
Location2012, 2nd Floor
Engineering Tracks
IP